1. Field of the Invention
The present invention relates to fabrication methods for terrace gate DMOS transistors. Specifically, the present invention relates to the alignment and spacing of the terrace oxide and the polysilicon gate.
2. Discussion of the Related Art
To reduce the conduction and switching losses in a MOSFET, it is desirable to reduce the specific ON resistance and the specific input capacitance. The purpose of the terrace gate is to reduce the capacitance between the gate and the source, thus allowing the DMOS device to switch faster. The gate capacitance is caused by the overlap of the polysilicon gate to the substrate. The polysilicon gate overlaps the substrate over the thin gate oxide and the thick terrace oxide. In a capacitor, the capacitance is inversely proportional to the separation of the plates. The terrace oxide separates the polysilicon from the substrate in the regions where no inversion layer is needed at the surface of the substrate, thus reducing the gate capacitance without affecting control of the channel. There is no channel directly beneath the terrace oxide.
However, in conventional DMOS terrace gate methods, the reduction in gate capacitance caused by introducing the terrace gate is somewhat offset by an increase in gate capacitance caused by gate dimension margins added for mask alignment, as discussed below.
FIGS. 1A through 1D illustrate a conventional DMOS terrace gate fabrication method. In FIG. 1A, an N- substrate 100 has a field oxide layer 101 formed on top. A photoresist layer 102 defines the terrace oxide. FIG. 1B illustrates the terrace oxide 101 after an etch back to the substrate 100.
As illustrated in FIG. 1C, after a gate oxide 103 growth and a polysilicon 104 deposition, a second photoresist mask 105 is formed. The photoresist mask 105 must be carefully aligned to the terrace oxide 101. The gate dimension (GD) represents the length of the gate which will be used for the channel region from a source 106 (FIG. 1D) in the DMOS transistor pairs. This dimension is very important in determining transistor threshold voltage, ON resistance, and other characteristics. The gate separation distance (GS) represents the required minimum polysilicon separation. Because the second photoresist mask 105 must be aligned to the existing terrace oxide 101, the gate dimension GD of the design is increased by a mask alignment tolerance. The mask alignment tolerance is approximately 0.2 to 0.3 microns in modern process technology.
Because the photoresist mask 105 must overlap the polysilicon edge 107 by at least a minimum alignment tolerance determined by photolithography, the lateral thickness of the polysilicon 104 around the terrace oxide places a minimum constraint on the gate dimension.
FIG. 1D illustrates a partial DMOS structure fabricated according to conventional techniques. The structure shown in FIG. 1D illustrates a two DMOS structure. FIG. 1D does not illustrate, for example, the interconnection of the polysilicon gates which occurs in other portions of the circuit layout.
Normally, the gate dimension (GD) of a conventional DMOS terrace gate cell is around 4 or 5 microns. Each alignment tolerance is around 0.2 or 0.3 microns, not including etch dimension changes and critical dimension variations. The total alignment margin which must be added to the gate dimension to accommodate for alignment becomes around 0.5 to 0.6 microns per side, or about 1.2 microns total in a 4 to 5 micron structure. Therefore, an overhead of over 30% is added in the lateral dimension to accommodate for the critical mask alignment. In two-dimensional circuit layout, where area is the metric of concern, dimension increases are squared to determine area increase due to margin. Thus, a 30% one-dimensional increase corresponds to a 69% area increase.
Moreover, the device geometries are decreasing in feature size more rapidly than photolithographic mask alignment tolerances. Therefore, as cell densities become higher, each 0.3 micron mask alignment becomes a higher percentage of the total pitch. All of the feature sizes are becoming compressed as the technology develops greater levels of miniaturization.
The need exists for a self-aligned method of forming DMOS terrace gates because the pitch sizes are reduced to less than the alignment margins, thus rendering it impossible to construct using photolithographic techniques while maintaining adequate performance, because there simply is not enough room to accommodate photolithographic alignments. Moreover, if the capacitance added by necessary photolithographic margins is greater than the reduction in gate capacitance caused by using the terrace gate, then terrace designs are no longer desirable. Many feature sizes are so small that this point of diminishing return has been reached.
As is apparent from the above-discussion, a need exists for a self-aligned terrace gate DMOS transistor fabrication method. In order to reduce conduction and switching losses in MOSFET power devices, the reduction of the on-resistance and reduction of input capacitance are desired. A need for reliable fabrication of uniform DMOS transistors exists. Reduction of cell pitch helps achieve these objectives.